1. Field of the Invention
The invention relates to a semiconductor layout structure and a designing method thereof, and more particularly, to a semiconductor layout structure including a cell width being a multiple of a poly pitch and a designing method thereof.
2. Description of the Prior Art
Semiconductor integrated circuits are one of the most important hardware used in the modern information society. A key design point of the semiconductor industry is to increase integration of integrated circuits, and therefore to use the area of integrated circuits (ICs) more efficiently. Generally speaking, ICs having complex functions are made up of many standard cells, each with basic functions. Since those standard cells are essential elements for constructing ICs, layout structures of those standard cells enormously affect the whole layout structure of the ICs.
Conventional standard cells can include different cell widths, and when the cell width is a multiple of the poly pitch, it is concluded that such standard cell is an on-grid layout structure. The on-grid layout structure improves the efficiency of placement and routing (P&R) for IC design. Additionally, in some software tool, it only takes the on-grid layout structure for placement and routing. In other words, different standard cells can be easily integrated into one chip when it include the on-grid layout structure. However, the cell width depends on the complexity of the standard cell: complex standard cell includes larger cell width. Furthermore, not all standard cells in the state-of-the-art include the on-grid layout structure.
Therefore it is still in need to provide a method for designing semiconductor layout structure such that standard cells of different cell widths can all include the on-grid layout structure.